TRA and RET take 2 machine cycles - all others take one. Repeated LBs are not executed. ATB is not executed if preceded by LB. EXC +/- 1 changes BL after the next instruction is executed. If BU toggles from 0 to 1, 2, or 3 (or vice versa), there is a 1 machine cycle delay until the availability of data referenced by the new value of B. B50xx/B60xx - after reset execution starts at 700. B50xx has 7 pages of ROM 0, 1, 2, 4, 5, 6, 7. B60xx has 8 pages of ROM 0-7. Subroutine page SR0 is page 0 and SR1 is page 1. B61xx - after reset execution starts at 000. B61xx has 14 pages of ROM 0-11, 14,15. Subroutine page SR0 is page 15 and SR1 is page 14. TRA 0,x is for transferring to or within SR0. If not already in one of the subroutine pages, it stores the return address. TRA 1,x transfers within a page, or to another page if followed by TL. In SR0 and SR1, TRA 0,x jumps to page 0 address x, and TRA 1,x jumps to page 1, address x. In all other pages, TRA 0,x stores the return address and jumps to page 0, address x and TRA 1,x jumps to address x in the current page. TL y sets the page register to y, so the next instruction executed is the next LFSR PC in page y - unless TRA or RET precedes the TL instruction. TRA 1,x followed by TL y jumps to page y, address x. *** TRA 0,x followed by TL y *** RET followed by TL y If TL y following a TRA or RET is jumped to directly, it is executed like a bare TL, jumping to the next LFSR PC in page y. Some instructions can set a flag that causes the next instruction to be ignored. ATB is never ignored. RAM is addressed using the B register. BU holds the upper 2 bits of B and BL holds the lower 4 bits. BU selects one of four RAM "registers" and BL selects a specific 4-bit word in that "register". ***B50xx RAM "register" 0 has 12 words and "registers" 1-3 have 11 words. ***B60xx RAM ***B61xx RAM B50xx has 7 pages of ROM (448 bytes): 0-2, 4-7. Subroutine block SR0 is page 0 and subroutine block SR1 is page 1. B60xx has 8 pages of ROM (512 bytes): 0-7. Subroutine block SR0 is page 0 and subroutine block SR1 is page 1. B61xx has 14 pages of ROM (896 bytes): 0-11, 14, 15. Subroutine block SR0 is page 15 and subroutine block SR1 is page 14. B6100 has 9 strobe drivers STR0-STR8, 10 segment drivers SEG1-10, 4 synchronized inputs, 4 non-synchronized inputs, clock frequency 70kHz +/- 30% Football: Digits left to right are STR0-STR6. Playfield columns from left to right are STR0-STR8. Playfield rows bottom to top are SEG8-10. LED digit strobes are set by B register. Only one strobe can be turned on at a time, but all can be turned off together. LED segments 1-7 come from RAM and segment 0 comes from the C flip flop. The carry flip flop is connected to the piezo. INSTRUCTIONS NOP 00 No operation. RSC 0D for B61xx, 39 for B60xx/B50xx Reset C flip flop. C=0 SC 0C for B61xx, 3B for B60xx/B50xx Set C flip flop. C=1 TC 01 Test C flip flop- next instruction is ignored if C flip flop is set. IGN=C LAX x (0-15) 4F-40 Loads 4-bit operand into accumulator. A=x ADX x (1-15) 6E-60 Adds 4-bit operand to accumulator. The next instruction is ignored if an overflow does not occur. A=A+x if not overflow, IGN=1 COMP 70-73 The accumulator is bitwise complemented. A=~A ATB 77 The accumulator is copied to the lower RAM address register BL. NOTE: ATB cannot be ignored, but is not executed if preceded by LB. BL=A LDA x (0-3) 50-53 The contents of the current memory address are copied into the accumulator. BU is replaced with the exclusive-OR of BU with x. There is a one instruction cycle delay between BU changing from 0 to 1, 2, or 3 (or vice versa) and the availability of the data referenced by the new value of B. A=M[BU,BL], BU=BU^x EXC x,0 (0-3) 58-5B The contents of the current memory address are exchanged with the contents of the accumulator. BU is replaced with the exclusive-OR of BU with x. There is a one instruction cycle delay between BU changing from 0 to 1, 2, or 3 (or vice versa) and the availability of the data referenced by the new value of B. A<->M[BU,BL], BU=BU^x EXC x,+1 (0-3) 54-57 Same as EXC x,0, except BL is incremented. There is a one instruction cycle delay until the availability of the data referenced by the new value of B. If BL increments to 8 or wraps around from 15 to 0, the next instruction is ignored. A<->M[BU,BL], BU=BU^x, BL=BL+1. If BL=8 or BL=0 then IGN=1 EXC x,-1 (0-3) 5C-5F Same as EXC x,+1, except BL is decremented. There is a one instruction cycle delay until the availability of the data referenced by the new value of B. If BL decrements to 15 from 0, the next instruction is ignored. A<->M[BU,BL], BU=BU^x, BL=BL-1. If BL=15 then IGN=1 ADD 72 The contents of the current memory address are added to the accumulator. A=A+M[BU,BL] ADD C 70 The contents of the current memory address are added to the accumulator. The C flip flop acts as a carry in and a carry out. A=A+M[BU,BL]+C, if overflow then C=1 ADD S 73 The contents of the current memory address are added to the accumulator. The next instruction is ignored if overflow does not occur. A=A+M[BU,BL], if not overflow then IGN=1 ADD C,S 71 The contents of the current memory address are added to the accumulator. The C flip flop acts as a carry in and a carry out. A=A+M[BU,BL]+C, if overflow then C=1 else IGN=1 TAM 7C-7F The contents of the current memory address are compared to the accumulator. The next instruction is ignored if they are equal. if A=M then IGN=1 LB x,y (0-3) (0,7-11 for B61xx, -10 for others) 3C-3F, 20-23, 2C-2F, 28-2B, 24-27, 1C-1F The B register is loaded; the upper 2 bits come from x and the lower four bits with y. In a sequence of LBs, the remainder are ignored after one is executed. There is a one instruction cycle delay between BU changing from 0 to 1, 2, or 3 (or vice versa) and the availability of the data referenced by the new value of B. BU=x, BL=y RSM x (1,2,4,8) 14-17 Resets one bit of the contents of the current memory address. M[BU,BL]&=~x SM x (1,2,4,8) 10-13 Sets one bit of the contents of the current memory address. M[BU,BL]|=x TM x (1,2,4,8) 08-0C Tests one bit of the contents of the current memory address. The next instruction is ignored if the bit is 0. IGN=~(M[BU,BL]&x) TL z (0-11 for B6100, 0-7 for others) 30-3B Transfers to the next LFSR address of page z. TL is never ignored. TRA 1,x followed by TL z results in a transfer to page z, address x. PU=z, PL=next PL TRA 0,x (0-63) 80-BF If the subroutine flag is not already set, the return address is saved. The subroutine flag is set. Transfer is made to address x in subroutine block SR0. Note: 2 instruction cycles. Used to transfer into or within subroutine block SR0. TRA 0,x followed by TL z results in a transfer to the subroutine with the return page address modified to z. if SR=0 then S=next P. SR=1, PU=SR0, PL=x TRA 1,x (0-63) CO-FF Transfer to address x in current page unless current page is SR0; in that case transfer to address x in SR1. TRA 1,x followed by TL z results in a transfer to page z, address x. Note: 2 instruction cycles. if current page = SRO then PU=SR1. PL=x RET 18-1B (no difference between opcodes) The subroutine flag is reset and the return address is loaded. RET followed by TL z loads the return address but replaces the page with z. Note: 2 instruction cycles. SR=0, P=S TKB 02 The next instruction is ignored if any key is down. if KB1 | KB2 | KB3 | KB4 then IGN=1 TDIN x (1-4) 04-07 The next instruction is ignored if input x is active. if Input x then IGN=1 READ 6F The one's complement of the keyboard input lines is added to the accumulator. The next instruction is ignored if overflow does not occur. A=A+~KB. If not overflow then IGN=1 KSEG 74 Disables the segment drivers. Note: must KSEG before LDSEG; LDSEG ORs in new data. SEGMENT=0 TKBS 03 Same as TKB except also does LDSEG; load segment drivers with the RAM word addressed by B and the C flip flop (delayed 2 instructions). Note: 2 instruction cycles. ATBZ 76 Same as ATB but segments are disabled, strobes are disabled, new strobe is loaded from BL. Note: 4 instruction cycles.