Not all address lines are always used.

EWRT (write enable) is not always used.

Pins 3, 22 and 23 are used to reroute the /CE signal from the internal ROM to an installed cart.
Pins 22 and 23 are shorted when no cart is installed; the ROMSEL signal comes from the CPU on pin 23 and goes to the
internal ROM on pin 22.

Other than cart G10, 24LC0x SEEPROM SDA=D0 and SCK=D1 when EWRT=0; D7=SDA when pin 2=0

1  GND
2  SEEPROM /RD
3  jumper to 22
4  VCC * SEEPROM SDA on G10
5  A15
6  A14
7  A13
8  A12
9  A11
10 A10
11 A9
12 A8
13 A7
14 A6
15 A5
16 A4
17 A3
18 A2
19 A1
20 A0
21 VCC
22 internal ROM /CE
23 ROMSEL (cart ROM /CE)
24 D7
25 D6
26 D5
27 D4
28 D3
29 D2
30 D1
31 D0
32 GND * SEEPROM SCL on G10
33 EWRT (/WE)
34 ERD (/OE)
35 VCC
36 A23
37 A22
38 A21
39 A20
40 A19
41 A18
42 A17
43 A16
44 GND